1. Field of the Invention
The present invention relates generally to microcomputer architecture and to a system and method for producing input/output expansion for single-chip microcomputers. More particularly, the present invention relates to a system for permitting addressable peripheral functions associated with dedicated internal addresses of a microcontroller to exist physically external to a microcontroller and yet interface to the program being executed by the microcontroller as if they were internal to the microcontroller.
2. Related Art
Soon after the development of the microprocessor, semiconductor process technology advanced to the point where it became possible to integrate enough Read Only Memory (ROM) and Random Access Memory (RAM) on a single chip, along with a Central Processing Unit (CPU) to make a useful single-chip microcomputer. These single-chip microcomputers are often referred to as microcontrollers. Typically, a microcontroller includes a ROM for storing one or more software programs, RAM for storage of variables used by the program(s) during operation, a CPU for performing various arithmetic and logical functions and a plurality of Input/Output (I/O) lines. These I/O lines are often viewed in groups of eight and the groups are referred to collectively as I/O ports, or simply ports. Sometimes individual I/O lines are referred to as port pins. Microcontrollers also often include on-chip peripheral functions such as timers, counters, serial or parallel communication channels, A/D converters, and D/A converters. Representative examples of microcontrollers described above are the well-known 68HC11 (manufactured by Motorola Corp.) and the 8051 family of microcontrollers (manufactured by Intel Corporation of Santa Clara, Calif., Signetics Corporation of Sunnyvale, Calif. (Signetics is also known as Phillips Semiconductor), and others). As a particular example, the 8052 microcontroller, a member of the 8051 microcontroller family, includes in addition to a CPU, a 256 byte RAM, an 8192 byte ROM, an interrupt controller, a full duplex Universal Asynchronous Receiver/Transmitter (UART), three 16 bit timer/counters, and four 8 bit general purpose I/O ports. FIG. 1 is a block diagram showing the architecture of the 8051.
The 8051 family uses what is called a Harvard architecture. That is, program code memory and data memory are separated into different address spaces. The 8051 family further distinguishes between internal data memory and external data memory. A map of internal data memory is shown in FIG. 2. The three portions of internal data memory are called the lower 128, the upper 128, and the SFR space. The SFR space can only be accessed directly, and any access to an SFR includes always having the SFR address on the instructions bus. Internal data memory addresses are eight bits wide which generally implies an address space of 256 locations. SFRs include the PORT latches, timers, peripheral controls and so on.
Microcontroller peripheral functions are typically controlled by accesses to (i.e., read and or write transactions with) a set of on-chip registers that provide control bits, flags and data transfer between the peripheral function and the on-chip CPU. These peripheral function control registers are typically dedicated internal addresses. They are designed that way to optimize performance. In the case of the 8051 family of microcontrollers, the dedicated internal addresses used to access the peripheral functions are called Special Function Registers (SFRs). Transactions with SFRs (i.e., reading from and writing to SFRs) are done completely internal to 8051 family microcontroller chips, with no external visibility. As shown in FIG. 2, the 8051 family architecture provides 128 dedicated internal addresses which are set aside for SFRs. Only a small number of these 128 addresses are typically used in any particular 8051 family device. For example, the 8052 device described above uses only 26 SFRs to handle all its peripheral functions. In summary, with respect to 8051 architecture microcontrollers, SFRs and external memory reside in different address spaces and the software required to access SFRs is different from the software necessary to access external memory. This architectural scenario exists for other microcontrollers as well.
When a microcontroller is used in a particular application, additional peripheral functions are typically added to the system in order to customize it. These additional peripheral functions are, of necessity added external to the microcontroller. If the microcontroller used in the system is an 8051 microcontroller, it is currently impossible to access these external peripheral functions using the high performance SFR access method. Instead, the external peripheral functions are required to be mapped to the External Data Memory space. Accessing the External Data Memory space is slow and cumbersome as compared to accessing the SFR space.
In order to illustrate the performance differential between accessing a peripheral function in SFR space and a similar peripheral function in External Data Memory space, two program segments that perform the same function are presented in Tables I and II below. Both program segments test a bit in a control register, and if set, each of the program segments then directs the reading of data from a Buffer Register followed by a store operation to a RAM-based variable. Table I shows how this function is accomplished in SFR space, and Table II shows how this function is presently accomplished when the control register of the peripheral function is in external data memory space.
TABLE I ______________________________________ JNB status.sub.-- flag, not.sub.-- done 2 cycles MOV variable, data.sub.-- register 1 cycle total cycles for conventional internal 3 cycles access ______________________________________
TABLE II ______________________________________ MOV DPTR, #status.sub.-- address 2 cycles MOVX A, @DPTR 2 cycles JNB acc.status.sub.-- flag, not.sub.-- done 2 cycles MOV DPTR, #data.sub.-- register.sub.-- address 2 cycles MOVX A, @DPTR 2 cycles MOV variable, A 1 cycles total cycles for conventional external 11 cycles access ______________________________________
Note that eleven machine cycles are required for the program segment using an external-memory-space-based status flag and data register, while only three machine cycles are used with an SFR-space-based status flag and data register. Additionally, it should be noted that the code density for the program segment using an external-memory space-based status flag is poor compared to the code density of a program segment using an SFR-space-based status flag.
In view of the significant performance gap between operations performed on internal data memory and external data memory, there is a need for a system and method to access physically external memory and I/O devices as if they were mapped into SFR space.
A system for treating external registers of peripheral functions as if they were a part of the internal fast access memory space of a microcontroller is disclosed in U.S. Pat. No. 4,878,174 issued to Watkins, et al. The disclosure of Watkins, et al., teaches the desirability of treating external memory, or peripheral device control registers, as if they were part of the internal fast access memory space. Watkins, et al., at col. 2, lines 39-45 describes "adding the registers associated with these dedicated functions to the internal register file of the microcomputer." FIG. 3 of Watkins, et al., shows the addition of a dedicated port to a microcontroller in order to effectively couple a corresponding external memory or peripheral control register to the internal bus of the microcontroller. More specifically, Watkins, et al., appear to teach adding a register, register address decoding logic, port pads and input/output buffers to the same substrate on which the microcontroller is formed. This dedicated port would then be coupled to an external dedicated logic block. However, not only does this approach require additional pins on the microcontroller and a special package to accommodate those pins, more importantly this approach requires a customized chip. This method also seems to be limited because over 800 additional pins would be required to implement the full set of available SFR addresses, and such packaging either does not exist or is too expensive to implement for a low-cost microcontroller system.
Although many peripheral functions in a system are added external to the microcontroller, continuing advances in semiconductor technology now permit the incorporation of some of these external peripheral functions onto the same substrate in which the microcontroller itself is formed. Generally, an ASIC design approach is used to produce such a microcontroller with a unique set of peripheral functions. ASIC design methodology can reduce the time to market for an IC, but the tradeoff is generally a less efficient logic and layout design than could have been achieved by skilled human IC designers. Although quick time to market is very important in this industry, a particularly troubling aspect of this design approach is the large chip size which results since manufacturing yield is inversely proportional to chip size. Also, it is difficult and time-consuming to simulate a large, complex design with currently existing software simulation tools.
Furthermore, microcontrollers of the type discussed herein are typically found in embedded applications. That is, unlike a computer system designed to communicate with a user, these microcontrollers often form a substantial part of a low-cost control system which does not have facilities for communicating with a user. This tends to make the debugging portion of a product development cycle more difficult. One solution created to address this problem is the in-circuit emulator (ICE). The ICE is typically comprised of hardware and software. The ICE permits the development engineer to monitor and analyze the activity of a microcontroller as it operates in a target system. Unfortunately, some of the commercially available microcontrollers do not provide a straightforward way to access data and signals that exist internal to the microcontroller. Consequently, microcontroller manufacturers responded by providing a special, more costly to produce, version of the microcontroller called a bond-out chip. The bond-out chip contained extra bonding pads, buffers, and signal interconnect, and typically required a different package. The bond-out chips can be used in an ICE so that activity internal to the microcontroller is easy to monitor.
A lower cost solution to the problem of observing internal activity of the microcontroller involves using a standard microcontroller, (i.e., not a bond-out chip) and recreating, external to the microcontroller, some of its I/O ports and registers. However, recreation of, for example, PORT0 and PORT2 for emulation of 8051 family microcontrollers has conventionally required a substantial amount of circuitry. For a discussion of circuitry used in supporting emulation of single-chip microcontrollers see U.S. Pat. No. 4,939,637 issued to Pawloski, and incorporated herein by reference as if fully set forth below.
What is needed is a system and method for treating memory and/or peripheral device control registers which are not integrated onto a single-chip microcomputer as if they were part of the internal address space. In this way read/write transactions with physically external memory and peripheral control registers can be accomplished with greater speed and higher code density. What is further needed is a system and method for expanding the amount of data memory that can be used by a microcontroller. What is still needed is a system and method for supporting emulation of single-chip microcontrollers. What is still further needed is a system and method for supporting low-cost, fast prototyping of ASIC microcontrollers.